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preliminary this document contains information on a product under development at advanced micro devices. the information is intended to help you evaluate this product. amd reserves the right to change or discontinue work on this proposed product without notice. publication# 21138 rev: e amendment/ 0 issue date: september 1997 AMMCL00XA 2 or 4 megabyte 3.0 volt-only flash miniature card distinctive characteristics n 2 or 4 mbytes of addressable flash memory n 2.7 v to 3.6 v, single power supply operation write and read voltage: 3.0 v C10/+20% no additional supply current required for v pp n fast access time 150 ns maximum access time n cmos low power consumption typical active read current: 35 ma (word mode) typical active erase/write current: 40 ma (word mode) typical standby current: 10 m a (4 mbyte); 5 m a (2 mbyte) n high write endurance guaranteed minimum 100,000 write/erase cycles per card more than 1,000,000 cycles per card typical n uniform sector architecture 64k byte individually useable sectors erase suspend/resume increases system level performance busy# and reset# signals n zero data retention power no power required to retain data n available in industrial temperature grade (C40 c to +85 c) n miniature card standard form factor true interchangeability 60-pad elastomeric connector supports multiple technologies sonic welded stainless steel case pcmcia type ii adapter available selectable byte- or word-wide configuration small form factor (38 mm x 33 mm x 3.5 mm) n 60 connection bus 16-bit data bus 25-bit address bus easy system integration low cost implementation low cost cards n consumer-friendly mechanicals user can easily insert and remove card, upgrade memory, and add applications n voltage level keying does not allow a 3 v card to plug into a 5 v system and vice versa single power supply design system does not need a separate program voltage supply; only one is necessary to read and write general description the miniature card is an expansion card that pro- vides a low cost, low power, high-performance, small form factor solution for data and file storage to the portable, handheld market, which includes audio, digital film, wireless, and pda (portable digital assistant) applications. miniature cards can be easily snapped into the back of an electronic system and can be readily removed and replaced by end users. amds 3 v flash miniature cards are manufactured using amds industry leading 3.0 volt-only, single-power-supply am29lv081 flash memory device, ensuring high reliability and excellent performance. the miniature card is less than 30% of the size of a pcmcia memory card. applications include digital voice recorders, pocket pcs and intelli- gent organizers, smart cellular telephones, voice and data messaging pagers, digital still cameras and por- table instrumentation equipment. the miniature card specification will be defined by pcmcia as of october 1997. the participating associ- ation members include major flash memory vendors and leading consumer electronics oems. the goal of the miniature card specification is to promote an open,
2 AMMCL00XA preliminary interoperable small-form-factor memory card standard. for more information on the miniature card specifica- tion, visit the pcmcia web site at http://www.pc-card.com. amd flash miniature cards can be read in either a byte-wide or word-wide mode, which allows for flexible integration into various system platforms. compatibility is assured at the hardware interface and software inter- change specification. the miniature card is also designed with low-cost and rugged handling in mind. the card contains virtually no control logic, which keeps cost and power consumption to a minimum. the miniature card is packaged in a sonic welded, stainless steel case that guarantees durability, provides good esd protection and ease of handling. the miniature card has extensive third-party support, including socket and connector solutions, software support from the major ftl software vendors, and pcmcia adapter solutions and programmer support. amd's miniature flash cards can be used for both code and data storage. since fast random access is pos- sible, code can be directly executed from the card, reducing the amount of system ram required. in addi- tion. amds flash technology offers unsurpassed endurance, data retention and reliability, eliminating the need for complex error correction and defect man- agement hardware and software. each flash sector provides a minimum of 100,000 cycles, and a typical card life of one million or more cycles. for more information, please contact your local amd sales office or visit our web site at http://www.amd.com/html/products/nvd/nvd.html. definitions table 1 lists the terms and definitions that may be used in conjunction with miniature card specifications. table 1. miniature card definitions term meaning ais acronym for attribute information structure. ais is a miniature card specification for storing miniature card attribute information. esd acronym for electrostatic discharge. esd is part of the miniature card physical test. fat acronym for file allocation table. using an fat is a common method for managing files in a dos-based system. flash a type of non-volatile memory that is both readable and writeable, but requires the media to be erased before it is rewritten. host any system that incorporates a miniature card socket. insertion, cold user perception: insertion of the miniature card when the host is off. host state: the host would be either off or in sleep mode, no bus activity is occurring, the host is non-operational by the user. the user inserts the miniature card and then presses a button to turn the host on before the system is operational. insertion, hot user perception: insertion of a miniature card when the host is running. host state: the host would be in running mode, bus activity is occurring, the host is operational by the user. the user inserts the card, the host recognizes it, and the host continues to be operational. note: hot insertion may require buffering on the host system for proper operation. insertion, pseudo hot user perception: insertion of a miniature card when the host is running. host state: the host would be in running mode, bus activity is occurring, the host is operational by the user. the user inserts the card, the host immediately powers off before the miniature card makes contact with the hosts internal bus. the user would then need to press a button to turn the host on for it to become operational. interface signals miniature card signals that make connection through the 60-pad connector area. jedec acronym for joint electronic device engineering council. miniature card backside the side of the miniature card that contains the latching mechanism. the backside is opposite the frontside. miniature card bottomside the side of the miniature card that contains the interface signals. the bottomside is opposite the topside.
AMMCL00XA 3 preliminary miniature card frontside the side of the miniature card that contains power, insertion, ground, voltage keys, and alignment notch. the frontside is opposite the backside. miniature card topside the side of the miniature card that contains the miniature card label. the topside is opposite the bottomside. pc card a memory or i/o card compatible with the pc card standard. pc card adapter the hardware that connects the miniature card 60 contact bus to the pc card 68 pin bus. this hardware can be mechanically implemented by following the pc card type ii specification. power/insertion signals the three signals on the frontside of the miniature card that provide ground, power and early detection of insertion. pull-ups resistors used to ensure that signals do not float when no device is driving them. removal, cold user perception: removal of a miniature card when the host is off. host state: the host would either be off or in sleep mode, no bus activity is occurring, the host is non-operational by the user. user would turn off the host, then remove the miniature card and then press a button to turn the host on for it to become operational again. removal, hot user perception: removal of the miniature card when the host is running. host state: the host would be in running mode, bus activity is occurring, the host is operational by the user. user removes the card, the host recognizes the event, and the host continues to be operational. removal, pseudo hot user perception: removal of the miniature card when the host is running. host state: the host would be in running mode, bus activity is occurring, the host is operational by the user. user removes the card, the host recognizes the event, the host immediately powers off before the miniature card removes contact with the hosts internal bus. the user would then need to press a button to turn the host on for it to be operational again. sector usually 64 kbytes. in word mode, a sector is 64 kwords. tuple an element of the pc card standard cis that provides card attribute information, and a link to the next tuple in a string of tuples. user insertable all miniature cards should be inserted into the host by the user without the need for any special tools. user removable this type of miniature card can be removed by the user without the need for any special tools. it contains programs and data that users may want to switch often. the use of this type of card is similar to a floppy disk. user non-removable this type of miniature card must be removed by the user with a special tool. it contains memory upgrades or boot program that users switches only when they require an upgrade. the use of this type of card is similar to a simm memory expansion or boot hard disk. xip acronym for execute-in-place, which refers to code that executes directly from a miniature card. table 1. miniature card definitions (continued) term meaning
4 AMMCL00XA preliminary figure 1. miniature card connector (card bottom view) note: refer to the physical dimensions section for more information. also refer to the mcif specification for detailed mechanical information, available on the web at http://www.mcif.org. table 2. amd flash miniature cards and flash devices family part number density no. of flash devices amd flash memory ammcl002awp 2 mbyte 2 am29lv081 ammcl004awp 4 mbyte 4 am29lv081 write protect switch (optional) pad 60 pad 31 pad 30 pad 1 v cc cins# gnd 3v/5v key alignment notch 21138e-1
AMMCL00XA 5 preliminary block diagram * 4 mbyte card only. not used on 2 mbyte card. ** 2 mbyte card: two am29lv081 devices, s0 and s1 4 mbyte card: four am29lv081 devices, s0...s3 note: on the 2 mbyte card, a20Ca24 are not connected. on the 4 mbyte card, a21Ca24 are not connected. connections not shown in this diagram are not connected internally. oe# busy# ry/by# a0-a20 decoder* cel# 100k 100k ceh# we# we# to all flash devices write protect switch cel0# ceh0# cel1# ceh1# a20 v cc 10k v cc v cc oe# to all flash devices d0-d7 d8-d15 reset# reset# to all flash devices a0-a19 ce# we# oe# d8-d15 v ss v cc reset# ry/by# s1** a0-a19 ce# we# oe# d0-d7 v ss v cc reset# ry/by# s2** a0-a19 ce# we# oe# d8-d15 v ss v cc reset# ry/by# s3** a0-a19 ce# we# oe# d0-d7 v ss v cc reset# ry/by# s0** v cc v cc 100k 100k 21138e-2
6 AMMCL00XA preliminary miniature card pad assignments a0Ca24 address a0 to a24 are the address bus lines that can address up to 32 mwords (64 mbytes). the address lines are word addressed. the miniature card specifi- cation does not require the miniature card to decode the upper address lines. a 2 mbyte miniature card that does not decode the upper address lines would repeat its address space every 2 mbytes. address 0h would access the same physical location as 200000h, 400000h, 600000h, etc. on the 2 mbyte cards, a20C a24 are not connected. on the 4 mbyte cards, a21Ca24 are not connected. d0Cd15 data lines d0 through d15 constitute the data bus. the data bus is composed of two bytes; the low byte is d0Cd7 and the high byte is d8Cd15. these lines are tristated when oe# is high. oe# oe# indicates to the card that the current bus cycle is a read cycle. the output enable access time (t oe ) is the delay from the falling edge of oe# to valid data at the output pins (assuming the addresses have been stable for at least t acc C t oe time). we# we# indicates to the card that the current bus cycle is a write cycle. the falling edge of we# (or ce#), which- ever occurs later, latches address information and the rising edge of we# (or ce#), whichever occurs first latches data/command information. vs1# voltage sense 1 signal. this signal is grounded. vs2# voltage sense 2 signal. this signal is left open or not connected. cel# cel# enables the low byte of the data bus (d0Cd7) on the card. ceh# ceh# enables the high byte of the data bus (d8Cd15) on the card. reset# reset# controls card initialization. when reset# transitions from a low state to a high state, the minia- ture card resets to the read state after a maximum delay of 20 m s. busy# busy# is a signal generated by the card to indicate the status of operations within the miniature card. when busy# is high, the miniature card is ready to accept the next command from the host. when busy# is low, the miniature card is busy and unable to accept most data operations from the host. in flash miniature cards the busy# signal is tied to the components ry/by# signal. cd# cd# is a grounded interface signal. after a miniature card has been inserted, cd# will be forced low. the card detect signal is located in the center of the second row of interface signals, and should be one of the last interface signals to connect to the host. do not confuse cd# with cins#. cins# cins# is a grounded signal on the front of the miniature card that is used for early detection of a card insertion. cins# makes contact on the host when the front of the card is inserted into the socket, before the interface signals connect. bs8# the bs8# (bus size 8) signal indicates to the minia- ture card that the host has an 8-bit bus. amd flash miniature cards ignore this signal (no internal con- nection). an 8-bit host must connect its d0Cd7 data lines to d8Cd15 on the miniature card to retrieve the upper (odd) byte. gnd ground v cc vcc is used to supply power to the card. nc no connect rfu reserved for future use
AMMCL00XA 7 preliminary ordering information standard products amd standard products are available in several packages and operating ranges. the order number (valid combination) is formed by a combination of the following: am mc 004 wp speed option miniature card memory card density 002 = 2 megabyte card 004 = 4 megabyte card amd a revision level write protect switch option wp = switch installed -150 l 3 v, single supply operation 2.7 v to 3.6 v, extended operating voltage i temperature range blank = commercial (0 c to +70 c) i = industrial (C40 c to +85 c)
8 AMMCL00XA preliminary interface signal assignments note: nc = no connect; rfu = reserved for future use. flash miniature card operations voltage sensing amd miniature cards provide two voltage sense signals for hosts that support multiple voltages. the multivoltage host can sense the voltage level of the miniature card and power up the card at that voltage. see table 3 for a description of the voltage sense signals. in addition to the voltage sense pins, there are also mechanical voltage keys on the miniature card that ensure the card can only be inserted into host systems that can supply the proper voltage levels to the card. refer to section 4.1.2 in the miniature card specifica- tion for more information on mechanical keying. table 3. voltage sense signals pad number signal name pad number signal name pad number signal name 1 a18 21 d12 41 a4 2 a16 22 d10 42 cel# 3 a14 23 d9 43 a1 4 nc24d044nc 5 ceh# 25 d2 45 nc 6 a11 26 d4 46 cd# 7 a9 27 rfu 47 a21 8 a8 28 d7 48 busy# 9 a6 29nc49we# 10 a5 30 nc 50 d14 11 a3 31 a19 51 rfu 12 a2 32 a17 52 d11 13 a0 33 a15 53 vs2# 14 nc 34 a13 54 d8 15 a24 35 a12 55 d1 16 a23 36 reset# 56 d3 17 a22 37 a10 57 d5 18 oe# 38 vs1# 58 d6 19 d15 39 a7 59 rfu 20 d13 40 bs8# 60 a20 miniature card power-up voltage vs1# vs2# 3 volt-only gnd open
AMMCL00XA 9 preliminary data accesses the miniature card has a 16-bit data bus that can accommodate word or byte accesses. by individually asserting cel# and ceh#, a host can access either byte. however, byte swapping (moving the high byte data to the low byte) is not supported. figure 2 shows the connections between the host and miniature card. the host system address lines range from a0Ca25, whereas the miniature card address lines range from a0Ca24. on the host, a0 and the byte/word line are sent to a decoder and output to cel# and ceh# on the miniature card. these two bits enable a single device for byte accesses and two devices for word accesses, as shown by the decoder truth table in figure 2. again, the miniature card address lines do not receive input from host address bit a0. in this document, all address references are card addresses , unless otherwise noted. table 4 shows the read/write modes for miniature cards. * not connected ** not connected on 2 mbyte card figure 2. host/card address connections word-wide operations the amd miniature card provide the flexibility to operate on data in a byte-wide or word-wide format. in word-wide operations, the low bytes are controlled with cel#. the high bytes are controlled with ceh#. refer to the block diagram for more information. byte-wide operations byte-wide data is available for read and write opera- tions (cel# = 0, ceh# = 1). even and odd bytes are stored in separate memory devices (for example, s0 and s1) and are accessed by controlling cel# and ceh#. the even byte is the low order byte and the odd byte is the high order byte of a 16-bit word. each memory sector or device pair must be addressed separately for erase operations. refer to the block diagram for more information. card detection each cd# (output) pin should be detected by the host system to determine if the memory card is adequately seated in the socket. cd# and cins# are internally tied to ground. if both bits are not detected, the system should indicate that the card must be re-inserted. data protection an optional mechanical write protect switch provides user-initiated write protection. when this switch is acti- vated, we# is internally forced high. the flash memory command register is disabled from accepting any write commands. this prevents the card from responding to any commands (for example, an autoselect com- mand). see figure 3. byte/word a0 a1 ceh# cel# a0 a24 a23* a24* a23 a22* a22 a21* 60-pad connector a2 a1 decoder decoder truth table input output a0 b/w cel# ceh# 0000 0101 1000 1110 a20** a21 card bus a25 21138e-3 host bus
10 AMMCL00XA preliminary figure 3. write protect switch (card right side view) in addition to card-level data protection, amd flash miniature cards offer several device-level data protec- tion features. device-level data protection amd flash memory devices offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power tran- sitions. during power up, each device automatically resets the internal state machine to the read mode. the control register architecture allows alteration of the memory contents only occurs after successful comple- tion of specific multi-bus cycle command sequences. amd flash memory devices also incorporates the fol- lowing features to prevent inadvertent write cycles resulting from v cc power-up and power-down transi- tions or system noise. low v cc write inhibit to avoid initiation of a write cycle during v cc power-up and power-down, the amd memory devices in the min- iature card lock out write cycles for v cc < v lko (see dc characteristics on page 22 for voltages). when v cc < v lko , the command register is disabled, all internal program/erase circuits are disabled, and the device resets to the read mode. the memory devices ignore all writes until v cc > v lko . the user must ensure that the control pins are in the correct logical state when v cc > v lko to prevent unintentional writes. write pulse glitch protection noise pulses of less than 5 ns (typical) on oe#, ce#, or we# will neither initiate a write cycle nor change the command registers. logical inhibit writing is inhibited by holding any one of oe# = v il , ce# = v ih , or we# = v ih . to initiate a write cycle ce# and we# must be a logical zero while oe# is a logical one. power-up write inhibit power-up of the device with ce# = we# = v il and oe# = v ih will not accept commands on the rising edge of we#. the internal state machine is automatically reset to the read mode on power-up. read mode two card enable (ce#) pins are available on the memory card. both ce# pins must be active low for word-wide read accesses. only one ce# is required for byte-wide accesses. the ce# pins select and deter- mine when to apply power to the high-byte and low-byte memory devices. the output enable (oe#) controls gating accessed data from the memory device outputs. refer to table 4. the miniature card automatically powers up in the read/reset state. in this case, a command sequence is not required to read data. standard microprocessor read cycles will retrieve array data. this default state ensures that no spurious alteration of the memory content occurs during the power transition. refer to the ac read characteristics and waveforms for the spe- cific timing parameters. output disable data outputs from the card are disabled when oe# is at a logic-high level. under this condition, outputs are in the high-impedance state. write enabled write disabled 21138e-1
AMMCL00XA 11 preliminary table 4. miniature card read/write modes notes: 1. unlisted access combinations are invalid and may return unexpected results. 2. x indicates a dont care value. erase operations the amd flash miniature card is organized as an array of individual devices. each am29lv081 device contains sixteen 64 kbyte sectors, for a total of 1 mbyte of memory space per device. flash technology allows any logical 1 data bit to be pro- grammed to a logical 0. the only way to reset bits to a logical 1 is to erase that entire memory sector or memory device. once a memory sector or memory device is erased, any address location may be pro- grammed. two or more devices may be erased concur- rently when additional i cc current is supplied to the card. however, erasing more than two devices concurrently is not typical in battery-powered applications, but may take place during procedures such as card testing. erase operations can be performed in several ways: n erase a single sector or multiple sectors in a device n erase a sector pair n erase multiple device pairs* n erase the entire card* * this operation is only feasible in solutions capable of supplying more than the specified miniature card supply current requirement (150ma) per system. each amd flash memory device pair can accept a maximum of 120ma supply current. the common memory space data contents are altered in a similar manner to writing to individual flash memory devices. an on-card address decoder acti- vates the appropriate flash device in the memory array. each device internally latches address and data during write cycles. refer to table 4. standby mode the amd flash devices are designed to accommodate low standby power consumption. in order to achieve standby mode, the ce# line must be deselected. in addition, while in the standby mode, data i/o pins remain in the high impedance state independent of the voltage level applied to the oe# input. see the dc characteristics section for more details on standby modes. deselecting ce# (ce# and reset# = v cc 0.3 v) puts the device into the i cc3 standby mode. if the device is deselected during an embedded algorithm operation, it continues to draw active power (i cc2 ) prior to entering the standby mode, until the operation is complete. when the device is again selected (ce# = v il ), active operations occur in accordance with the ac timing specifications. automatic sleep mode advanced power management features such as the automatic sleep mode minimize flash device energy consumption. this is extremely important in bat- tery-powered applications. the amd memory devices automatically enable the low-power, automatic sleep mode when addresses remain stable for 300 ns. auto- matic sleep mode is independent of the ce#, we#, and oe# control signals. typical sleep mode current draw from each device is < 1 m a. standard address access timings provide new data when addresses are function ceh# cel# we# oe# d8Cd15 d0Cd7 read mode word access l l h l high byte data low byte data low byte access h l h l high-z low byte data high byte access l h h l high byte data high-z write mode word access l l l h high byte data low byte data low byte access h l l h high-z low byte data high byte access l h l h high byte data high-z standby mode standby h h x x high-z high-z
12 AMMCL00XA preliminary changed. while in sleep mode, output data is latched and always available to the system. command definitions each memory device contains a command register, which is a latch that saves address, commands, and data information used by the state machine and memory array. the state machine is active when v cc is greater than v lko (2.3 - 2.5 v). this is required for valid program and erase operations. when write enable (we#) and appropriate ce# signals are at a logic-low level, and output enable (oe#) is at a logic-high, the command register is enabled for write operations. the falling edge of we# or ce#, whichever occurs later, latches address infor- mation and the rising edge of we# or ce#, whichever occurs first, latches data/command information. commands are accomplished by writing non-specific address and specific data sequences into the com- mand register of accessed flash memory devices. writing incorrect address and data values or writ- ing them in the improper sequence will reset the device to the read mode. the byte-wide commands are defined in tables 6 and 7; word-wide commands are defined in table 5. note that the erase suspend (b0h) and erase resume (30h) commands are valid only while the sector erase operation is in progress. autoselect operation a host system or external card reader/writer can deter- mine the on-card manufacturer and device i.d. codes. codes are available after writing the 90h command to the command register of a memory device, as shown in tables 5 through 7. when the autoselect command is issued to card address 00000h, the miniature card returns the manufacturer i.d. if the autoselect command is issued to card address 00001h, the minia- ture card provides the device i.d. to terminate the autoselect operation, the read/reset command sequence must be written to the same device. the autoselect command operates only if the card is not write protected.
AMMCL00XA 13 preliminary table 5. word command definitions legend: x = dont care ra = address of the memory location to be read. rw = data read from location ra during read operation. pa = address of the memory location to be programmed. addresses are latched on the falling edge of the we# pulse. pw = data to be programmed at location pa. data is latched on the rising edge of we#. sa = address of the sector to be erased. refer to table 8 for sector addresses. notes: 1. write protect must not be enabled for proper operation of all commands. no command required for reading array data, and can thus be done with write protect enabled. 2. during word addressing, cel# = 0, ceh# = 0, and address is applied to memory device pair 0 (s0 and s1). on 4 mbyte cards, address for memory device pair 1 = (addr) + 200000h, and address is applied to memory device pair 1 (s2 and s3). for host-to-card address bit connections, see figure 2. 3. all values are in hexadecimal. 4. the last bus cycle in an autoselect command sequence is a read operation. 5. word = high byte + low byte. 6. address bits = x = dont care for all commands except for read address (ra), program address (pa), and sector address (sa). 7. the erase suspend command is valid only during a sector erase operation. refer to sector erase suspend. 8. the erase resume command is valid only during the erase suspend mode. 9. see table 4 for bus operations. embedded command sequence (note 1) bus cycles (notes 2C9) first second third fourth fifth sixth addr data addr data addr data addr data addr data addr data read 1 ra rw reset 1 xxxx f0f0 autoselect manufacturer id (note 4) 4 xxxx aaaa xxxx 5555 xxxx 9090 xx00 0101 autoselect device id (note 4) 4 xxxx aaaa xxxx 5555 xxxx 9090 xx01 3838 word write 4 xxxx aaaa xxxx 5555 xxxx a0a0 pa pw device erase 6 xxxx aaaa xxxx 5555 xxxx 8080 xxxx aaaa xxxx 5555 xxxx 1010 sector erase 6 xxxx aaaa xxxx 5555 xxxx 8080 xxxx aaaa xxxx 5555 sa 3030 sector erase suspend (note 7) 1 xxxx b0b0 sector erase resume (note 8) 1 xxxx 3030 cycles
14 AMMCL00XA preliminary table 6. even byte command definitions note for table 6: during even (low) byte accesses, cel# = 0, ceh# = 1. address is applied to memory device 0 (s0). on 4 mbyte cards, address for memory device 2 (s2) = (addr) + 200000h. table 7. odd byte command definitions note for table 7: during odd (high) byte accesses, cel#= 1, ceh# = 0, and address is applied to memory device 1 (s1). on 4 mbyte cards, address for memory device 3 (s3) = (addr) + 200000h + 100000h. legend for tables 6 and 7: x = dont care ra = address of the memory location to be read. rw = data read from location ra during read operation. pa = address of the memory location to be programmed. addresses are latched on the falling edge of the we# pulse. pw = data to be programmed at location pa. data is latched on the rising edge of we#. sa = address of the sector to be erased. refer to table 8 for sector addresses. notes for tables 6 and 7: 1. write protect must not be enabled for proper operation of all commands. no command required for reading array data, and can thus be done with write protect enabled. 2. for host-to-card address bit connections, see figure 2. 3. all values are in hexadecimal. 4. the last bus cycle in an autoselect command sequence is a read operation. 5. address bits = x = dont care for all commands except for read address (ra), program address (pa), and sector address (sa). 6. the erase suspend command is valid only during a sector erase operation. refer to sector erase suspend. 7. the erase resume command is valid only during the erase suspend mode. 8. see table 4 for bus operations. embedded command sequence (note 1) bus cycles (notes 2C8) first second third fourth fifth sixth addr data addr data addr data addr data addr data addr data read 1 ra rd reset 1 xxxx xxf0 autoselect manufacturer id (note 4) 4 xxxx xxaa xxxx xx55 xxxx xx90 xx00 xx01 device id (note 4) 4 xxxx xxaa xxxx xx55 xxxx xx90 xx01 xx38 byte write 4 xxxx xxaa xxxx xx55 xxxx xxa0 pa pd device erase 6 xxxx xxaa xxxx xx55 xxxx xx80 xxxx xxaa xxxx xx55 xxxx xx10 sector erase 6 xxxx xxaa xxxx xx55 xxxx xx80 xxxx xxaa xxxx xx55 sa xx30 sector erase suspend (note 6) 1 xxxx xxb0 sector erase resume (note 7) 1 xxxx xx30 embedded command sequence (note 1) bus cycles (notes 2C8) first second third fourth fifth sixth addr data addr data addr data addr data addr data addr data read 1 ra rd reset 1 xxxx xxf0 autoselect manufacturer id (note 4) 4 xxxx aaxx xxxx 55xx xxxx 90xx xx00 01xx autoselect device id (note 4) 4 xxxx aaxx xxxx 55xx xxxx 90xx xx01 38xx byte write 4 xxxx aaxx xxxx 55xx xxxx a0xx pa pdxx device erase 6 xxxx aaxx xxxx 55xx xxxx 80xx xxxx aaxx xxxx 55xx xxxx 10xx sector erase 6 xxxx aaxx xxxx 55xx xxxx 80xx xxxx aaxx xxxx 55xx sa 30xx sector erase suspend (note 6) 1 xxxx xxb0 sector erase resume (note 7) 1 xxxx xx30 cycles cycles
AMMCL00XA 15 preliminary table 8. memory sector addresses notes: 1. for word addressing, devices 0 and 1 (s0 and s1) together form memory device pair 0; devices 2 and 3 (s2 and s3) form memory device pair 1. refer to the block diagram for device connections. 2. card address bits range from a0 to a19. host address bits range from a0 to a20. host address bit a0 is used for controlling the cel# and ceh# inputs to the card. refer to figure 2 for host-to-card address bit connections. sector card address bits device 0 and/or 1 (note 1) device 2 and/or 3 (note 1) a19 a18 a17 a16 card address range card address range 0 0 0 0 0 00000hC0ffffh 100000hC10ffffh 1 0 0 0 1 10000hC1ffffh 110000hC11ffffh 2 0 0 1 0 20000hC2ffffh 120000hC12ffffh 3 0 0 1 1 30000hC3ffffh 130000hC13ffffh 4 0 1 0 0 40000hC4ffffh 140000hC14ffffh 5 0 1 0 1 50000hC5ffffh 150000hC15ffffh 6 0 1 1 0 60000hC6ffffh 160000hC16ffffh 7 0 1 1 1 70000hC7ffffh 170000hC17ffffh 8 1 0 0 0 80000hC8ffffh 180000hC18ffffh 9 1 0 0 1 90000hC9ffffh 190000hC19ffffh 10 1 0 1 0 a0000hCaffffh 1a0000hC1affffh 11 1 0 1 1 b0000hCbffffh 1b0000hC1bffffh 12 1 1 0 0 c0000hCcffffh 1c0000hC1cffffh 13 1 1 0 1 d0000hCdffffh 1d0000hC1dffffh 14 1 1 1 0 e0000hCeffffh 1e0000hC1effffh 15 1 1 1 1 f0000hCfffffh 1f0000hC1fffffh
16 AMMCL00XA preliminary amd flash memory program and erase operations to simplify program and erase operations, amd flash memory devices include embedded algorithms (embedded erase algorithm and embedded program algorithm) that allow the host to simply issue a com- mand, after which it is free to perform other tasks. the host then only needs to monitor appropriate status bits to determine when the operation is complete. embedded erase algorithm when erasing a sector or device, the embedded erase algorithm does not require the host to first entirely pre-program the device. upon executing the embedded erase command sequence, the addressed memory sector or memory device automatically writes and verifies the entire memory device or memory sector for an all 0 data pattern. the system is not required to provide any controls or timing during these operations. when the memory sector or memory device is auto- matically verified to contain an all 0 pattern, a self-timed chip erase-and-verify begins. the erase and verify operations are complete when the data on d7 (d15 on the odd byte) of the memory sector or memory device is 1 (see write operation status section), at which time the device returns to the read mode. the system is not required to provide any control or timing during these operations. if a reset command is issued while the erase operation is in progress, the erase operation will stop, and the data in that device will be undefined. in that case, restart the erase on that sector and allow it to complete. when using the embedded erase algorithm, the erase automatically terminates when adequate erase margin has been achieved for the memory array (no erase verify command is required). the embedded erase command sequence is a command only operation that stages the memory sector or memory device for automatic electrical erasure of all bytes in the array. the automatic erase begins on the rising edge of the we# and terminates when the data on d7 (d15 on the odd byte) of the memory sector or memory device is 1 (see write operation status section) at which time the device returns to the read mode. please note that for the memory device or memory sector erase operation, data polling may be performed at any address in that device or sector. figure 4 and table 9 illustrate the embedded erase algorithm, a typical command string and bus operations. as described earlier, once the memory sector in a device or memory device completes the embedded erase operation, it returns to the read mode and addresses are no longer latched. therefore, the device requires that a valid address input to the device is supplied by the system at this particular instant of time. otherwise, the system will never read a 1 on d7 (d15 on the odd byte). a system designer has the following choices to implement the embedded erase algorithm: 1. the host may keep the sector address (within any of the sectors being erased) valid during the entire embedded erase operation. 2. once the system executes the embedded erase command sequence, the host may remove the ad- dress from the device and perform other tasks. the host is required to keep track of the valid sector ad- dress by loading it into a temporary register. when the host comes back to data poll the device, it must reassert the same address. 3. the host may monitor busy# (ry/by#) to deter- mine the status of the embedded algorithm in progress. a 0 indicates that the device is busy; a 1 indicates that the algorithm is complete. sector erase sector erase is a six bus cycle operation. there are two unlock write cycles. these are followed by writing the set-up command. two more unlock write cycles are then followed by the sector erase command. the sector address (any address location within the desired sector) is latched on the falling edge of we# (or ce#), whichever occurs later, while the data is latched on the rising edge of we# (or ce#) pulse, whichever occurs first. a time-out of 80 m s from the rising edge of the last sector erase command will initiate the sector erase command. multiple sectors can be specified for erase by writing the six bus cycle operation as described above and then following it by additional writes of the sector erase command to addresses of other sectors to be erased. the time between sector erase command writes must be less than 80 m s, otherwise that command will not be accepted. it is recommended that processor interrupts be disabled during this time to guarantee this condition. the interrupts can be re-enabled after the last sector erase command is written. a time-out of 80 m s from the rising edge of the last we# (or ce#) will initiate the ex- ecution of the sector erase command(s). if another falling edge of the we# (or ce#) occurs within the 80 m s time-out window, the timer is reset. during the 80 m s window, any command other than sector erase or erase suspend written to the device will reset the de- vice back to read mode. once the 80 m s window has timed out, only the erase suspend command is recog- nized. note that although the reset command is not recognized in the erase suspend mode, the device is available for read or program operations in sectors that are not erase suspended. the erase suspended and erase resume commands may be written as often as required during a sector erase operation. hence, once erase has begun, it must ultimately complete unless
AMMCL00XA 17 preliminary hardware reset is initiated. loading the sector erase registers may be done in any sequence and with any number of sectors (0 to 15). a reset command issued after the device has begun execution stops the erase operation, but the data in the sector will be undefined. in that case, restart the erase on that sector and allow it to complete. the automatic sector erase begins after the 80 m s time out from the rising edge of the we# (or ce# ) pulse for the last sector erase command pulse and terminates when the data on d7 is 1 (see write operation status section) at which time the device returns to read mode. data polling must be performed at an address within any of the sectors being erased. if data polling or the toggle bit indicates the device has been written with a valid sector erase command, d3 may be used to determine if the sector erase timer window is still open. if d3 is high (1), the internally controlled erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase operation is completed as indicated by the data polling or toggle bit. if d3 is low (0), the device will accept additional sector erase commands. to be certain the command has been accepted, the software should check the status of d3 following each sector erase command. if d3 was high on the second status check, the command may not have been accepted. it is recommended that the user guarantee the time between sector erase command writes be less than 80 m s by disabling the processor interrupts just for the duration of the sector erase (30h) commands. this approach will ensure that sequential sector erase command writes will be written to the device while the sector erase timer window is still open. figure 4 illustrates the embedded erase algorithm using typical command strings and bus operations. table 9. embedded erase algorithm figure 4. embedded erase algorithm note: the latest release of the software drivers for amd miniature cards and devices may be downloaded from the amd web site at http://www.amd.com. embedded program algorithm the embedded program setup is a four bus cycle oper- ation that stages the addressed memory location or memory device for automatic programming. once the embedded program setup operation is per- formed, the next we# pulse causes a transition to an active programming operation. addresses are inter- nally latched on the falling edge of the we# (or ce# ) pulse. data is internally latched on the rising edge of the we# pulse. the rising edge of we# also begins the programming operation. the system is not required to provide further control or timing. the device will auto- matically provide an adequate internally generated write pulse and verify margin. the automatic program- ming operation is completed when the data on d7 of the addressed memory sector or memory device is equivalent to data written to this bit (see write opera- tion status section) at which time the device returns to the read mode (no write verify command is required). addresses are latched on the falling edge of we# (or ce# ) during the embedded program command execu- tion and hence the system is not required to keep the addresses stable during the entire programming opera- tion. however, once the device completes the embedded program operation, it returns to the read mode and addresses are no longer latched. since a verify valid data must occur on d7, at this particular instant, the system is required to supply a valid address input to the device. a system designer has three choices to implement the embedded programming algorithm: bus operation command comments standby wait for v cc ramp write embedded erase command sequence 6 bus cycle operation read data poll or check busy# (ry/by#) to verify erasure write embedded erase command sequence (see tables 5C7) data poll from device or wait for busy# (ry/by#) start erasure complete 21138e-5
18 AMMCL00XA preliminary 1. the system (cpu) keeps the address valid during the entire embedded programming operation, or 2. once the system executes the embedded pro- gramming command sequence, the cpu takes away the address from the device and becomes free to do other tasks. in this case, the cpu is re- quired to keep track of the valid address by loading it into a temporary register. when the cpu comes back for performing data polling, it should reassert the same address. 3. the host may monitor busy# (ry/by#) to deter- mine the status of the embedded algorithm in progress. a 0 indicates that the device is busy; a 1 indicates that the algorithm is complete. however, since the embedded programming operation takes only 9 m s typically, it may be easier for the cpu to keep the address stable during the entire embedded programming operation instead of reasserting the valid address during data polling. any commands written to the device during this period will be ignored. figure 5 and table 10 illustrate the embedded program algo- rithm, a typical command string, and bus operation. table 10. embedded program algorithm figure 5. embedded program algorithm reset command the device will automatically power up in the read/re- set state. in this case, a command sequence is not re- quired to read data. standard microprocessor cycles will retrieve array data. this default value ensures that no spurious alteration of the memory content occurs during the power transition. refer to the ac character- istics section for the specific timing parameters. the reset operation is initiated by writing the read/reset command sequence into the command register. micro- processor read cycles retrieve array data from the memory. the device remains enabled for reads until the command register contents are altered. sector erase suspend the erase suspend command allows the user to inter- rupt a sector erase operation and then perform data read or programs in a sector not being erased. this command is applicable only during the sector erase operation, which includes the time-out period for sector erase. the erase suspend command will be ignored if written during the execution of the chip erase opera- tion or embedded program algorithm (but will reset the chip if written improperly during the command se- quences.) writing the erase suspend command during the sector erase time-out results in immediate termina- tion of the time-out period and suspension of the erase operation. once in erase suspend, the device is avail- bus operation command comments standby wait for v cc ramp write embedded program command sequence 3 bus cycle operation write program address/data 1 bus cycle operation read data poll or check busy# (ry/by#) to verify program 21138e-6 write embedded write command sequence per tables 5C7 verify data n y data poll device or wait for busy# (ry/by#) y increment address n start completed last address
AMMCL00XA 19 preliminary able for read (note that in the erase suspend mode, the reset/read command is not required for read opera- tions and is ignored) or program operations in sectors not being erased. any other command written during the erase suspend mode will be ignored, except for the erase resume command. writing the erase resume command resumes the sector erase operation. the ad- dresses are dont cares when writing the erase sus- pend or erase resume command. when the erase suspend command is written during a sector erase operation, the chip will take between 0.1 m s and 20 m s to actually suspend the operation and go into erase suspended read mode (pseudo-read mode), at which time the user can read or program from a sec- tor that is not erase suspended. reading data in this mode is the same as reading from the standard read mode, except that the data must be read from sectors that have not been erase suspended. successively reading from the erase-suspended sec- tor while the device is in the erase-suspend-read mode will cause d2 to toggle. polling d2 on successive reads from a given sector provides the system the ability to determine if a sector is in erase suspend. after entering the erase-suspend-read mode, the user can program the device by writing the appropriate com- mand sequence for byte program. this program mode is known as the erase suspend-program mode. again, programming in this mode is the same as programming in the regular byte program mode, except that the data must be programmed to sectors that are not erase sus- pended. successively reading from the erase sus- pended sector while the device is in the erase suspend-program mode will cause d2 to toggle. com- pletion of the erase suspend operation can be deter- mined two ways: n checking the status of the toggle bit d2 n checking the status of the ry/by# pin to resume the operation of sector erase, the resume command (30h) should be written. any further writes of the resume command at this point will be ignored. however, another erase suspend command can be written after the device has resumed sector erase op- erations. write operation status table 11 shows the status bit states for device program and erase operations. data pollingd7 (d15 on odd byte) the miniature card features data polling as a method to indicate to the host system that the embedded algo- rithms are in progress or completed. during the embedded program algorithm, an attempt to read the device will produce the compliment of the data last written to d7. upon completion of the embed- ded program algorithm, an attempt to read the device will produce the true data last written to d7. note that just at the instant when d7 switches to true data, the other bits, d6Cd0, may not yet be true data. however, they will all be true data on the next read from the de- vice. please note that data polling (d7) may give an inaccurate result when an attempt is made to write to a protected sector. during an embedded erase al- gorithm, an attempt to read the device will produce a 0 at the d7 output. upon completion of the embedded erase algorithm, an attempt to read the device will produce a 1 at d7. note: d7 is rechecked even if d5 = 1 because d7 may change simultaneously with d5. figure 6. data polling algorithm start dq7 = data? yes no no dq5 = 1? no yes dq7 = data? yes fail pass 21138e-7
20 AMMCL00XA preliminary table 11. hardware sequence flags notes: 1. performing successive read operations from the erase-suspended sector will cause d2 to toggle. 2. performing successive read operations from any address will cause d6 to toggle. 3. reading the byte address being programmed while in the erase-suspend program mode will indicate logic 1 at the d2 bit. however, successive reads from the erase-suspended sector will cause d2 to toggle. busy# (ry/by#ready/busy) the busy# signal indicates to the host the status of operations within the miniature card. the busy# signal is tied to the components ry/by# pins. the ry/by# signal from amd flash devices in the miniature card indicate that the embedded algo- rithms are either in progress or have been completed. if the output is low, the device is busy with either a program or erase operation. if the output is high, the device is ready to accept any read/write or erase op- eration. when the ry/by# pin is low, the device will not accept any additional program or erase com- mands with the exception of the erase suspend com- mand. if a flash device is placed in an erase suspend mode, the ry/by# output will be high. refer to the section sector erase suspend for more infor- mation. word-wide programming the word-wide programming sequence will be as usual per table 5. the program word command is a0a0h. each byte is independently programmed. for example, if the high byte of the word indicates the successful completion of programming via one of its write status bits such as d15, software polling should continue to monitor the low byte for write com- pletion and data verification, or vice versa. during the embedded programming operations the device exe- cutes programming pulses in 9 m s increments. word-wide sector erasing the word-wide sector erasing of a memory device pair is similar to word-wide programming. the erase word command is a six-bus-cycle command sequence (see table 5). each sector is independently erased and verified. word-wide erasure reduces total erase time when compared to byte erasure. each flash memory device in the card may erase at different rates. there- fore, each device (byte) must be verified separately. status d7 d6 d5 d3 d2 in progress byte program in embedded program algorithm d7 toggle 0 0 1 embedded erase algorithm 0 toggle 0 1 toggle erase suspended mode erase suspend read (erase suspended sector) 1100 toggle (note 1) erase suspend read (non-erase suspended sector) data data data data data erase suspend program (non-erase suspended sector) d7 toggle (note 2) 01 1 (note 3) exceeded time limits byte program in embedded program algorithm d7 toggle 1 0 1 program/erase in embedded erase algorithm 0 toggle 1 1 n/a erase suspended mode erase suspend program (non-erase suspended sector) d7 toggle 1 1 n/a
AMMCL00XA 21 preliminary absolute maximum ratings storage temperature . . . . . . . . . . . . . C40 c to +90 c ambient temperature with power applied . . . . . . . . . . . . . . C40 c to +85 c voltage at all pins (note 1) . . . . C0.5 v to v cc +0.5 v v cc (note 1) . . . . . . . . . . . . . . . . . . . . C0.5 v to 3.6 v output short circuit current (note 2) . . . . . . 200 ma notes: 1. minimum dc voltage on input or i/o pins is C0.5 v. during voltage transitions, inputs may overshoot v ss to C2.0 v for periods of up to 20 ns. maximum dc voltage on output and i/o pins is v cc + 0.5 v. during voltage transitions, outputs may overshoot to v cc + 2.0 v for periods up to 20ns. 2. no more than one output shorted at a time. duration of the short circuit should not be greater than one second. conditions equal v out = 0.5 v or 3.6 v, v cc = v ccmax . these values are chosen to avoid test problems caused by tester ground degradation. this parameter is sampled and not 100% tested, but guaranteed by characterization. 3. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the de- vice at these or any other conditions above those indi- cated in the operational sections of this specification is not implied. exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. operating ranges commercial devices case temperature (t c ). . . . . . . . . . . . . .0 c to +70 c industrial (i) devices case temperature (t c ). . . . . . . . . . . .C40 c to +85 c v cc supply voltages AMMCL00XAwp-150 . . . . . . . . . . . . +2.7 v to +3.6 v operating ranges define those limits between which the functionality of the device is guaranteed.
22 AMMCL00XA preliminary dc characteristics notes: 1. v cc = 2.7 v to 3.6 v. 2. supply current is a max rms value. read frequency = 5 mhz. connector dc specifications notes: 1. this current is a minimum that the connector should withstand, and a maximum that the host should provide. 2. on the host, these specifications must be met for one conducting channel on elastomeric connectors. card and pad capacitance notes: 1. sampled, not 100% tested. 2. test conditions t a = 25 c, f = 1.0 mhz. parameter symbol parameter description test conditions min max unit i li input leakage current v in = v ss to v cc, v cc = v cc max 5 m a i lo output leakage current v in = v ss to v cc, v cc = v cc max 5 m a i ccs v cc standby current cel#, ceh#, reset# = v cc 0.3 v v cc = 3.6v; v in = v ss or v cc 2 mbyte 30 m a 4 mbyte 40 m a i cc v cc supply current, word mode (note 2) reset# = v ih ; cel# and ceh# = v il read 40 ma write 60 ma v il input low voltage C0.5 0.8 v v ih input high voltage 0.7 v cc v cc + 0.5 v v ol output low voltage i out = 5.8 ma 0.45 v v oh output high voltage i out = C2.0 ma 0.85 v cc v v lko low v cc lock-out voltage 2.3 2.5 v parameter min max units interface signal resistance (note 2) 2.0 w interface signal current (notes 1, 2) 125 ma power/insertion signal resistance 0.060 w power/insertion signal current (note 1) 500 ma parameter symbol parameter description test conditions max unit c card card input capacitance 40 pf c host system load capacitance 120 pf c i/o i/o capacitance d0-d15 40 pf
AMMCL00XA 23 preliminary ac characteristics read-only operations parameter symbol parameter description -150 unit jedec standard t avav t rc read cycle time min 150 ns t elqv t ce chip enable access time max 150 ns t avqv t acc address access time max 150 ns t glqv t oe output enable access time max 50 ns t elqx t lz chip enable to output in low-z min 5 ns t ehqz t df chip disable to output in high-z max 30 ns t glqx t olz output enable to output in low-z min 5 ns t ghqz t df output disable to output in high-z max 30 ns t axqx t oh output hold from first of address, ce#, or oe# change min 5 ns t ready reset# pin low to read mode max 20 m s
24 AMMCL00XA preliminary ac characteristics write operations (erase/program) parameter symbols parameter description -150 unit jedec standard t avav t wc write cycle time min 150 ns t wlwh we# pulse width min 50 ns t elgl t elwl ce# setup time to we# or oe# active min 0 ns t avgl t avwl address setup time to we# or oe# active min 0 ns t dvwh data setup time to we# inactive min 50 ns t whdx data hold time from we# inactive min 0 ns t whax address hold time from we# inactive min 0 ns t wheh ce# hold time from we# inactive min 0 ns t rp reset# pulse width min 500 ns t busy program/erase valid to ry/by# delay min 90 ns t whwh1 programming operation typ 9 max 300 m s t whwh2 sector erase operation typ 1.5 max 15 s
AMMCL00XA 25 preliminary key to switching waveforms switching waveforms figure 7. ac waveforms for read operations must be steady may change from h to l may change from l to h does not apply dont care, any change permitted will be steady will be changing from h to l will be changing from l to h changing, state unknown center line is high- impedance off state waveform inputs outputs ks000010 t avav t avqv t avgl t ehqx oe# cel#/ceh# d0Cd15 valid data t elgl t elqv t elqnz t ghqz t axqx t ghqx t glqnz t glqv a0Ca25 21138e-8
26 AMMCL00XA preliminary switching waveforms figure 8. ac waveforms for write operations figure 9. ac waveforms for data polling during embedded algorithm operations t avav we# cel#/ceh# d0Cd15 t dvwh a0Ca25 t wlwh t avwl t wheh t whax t whdx valid data t elwl 21138e-9 d0Cd7 valid data t ch t oeh t oe t ce t whwh1 or t whwh2 d7= valid data high z ce# oe# we# t oh d7# d0Cd6=invalid *d7=valid data (the device has completed the embedded operation). * 21138e-10 d0Cd6 t df d7
AMMCL00XA 27 preliminary switching waveforms figure 10. ry/by# timing diagram during program/erase operations figure 11. reset# timing diagram ce# we# ry/by# t busy entire programming or erase operations the rising edge of the last we# signal 21138e-11 reset# 21138e-12 t ready t rp
28 AMMCL00XA preliminary ac characteristics-alternate ce# controlled writes write/erase/program operations notes: 1. rise/fall time 10 ns. 2. maximum specification not needed due to the internal stop timer that will stop any erase or write operation that exceed the device specification. 3. card enable controlled programming: flash programming is controlled by the valid combination of the card enable (ce1#, ce2#) and write enable (we#) signals. for systems that use the card enable signal(s) to define the write pulse width, all setup, hold, and inactive write enable timing should be measured relative to the card enable signal(s). 4. under worst case condition of 90 c, vcc = 2.7 v, 100,000 cycles. excludes system level overhead, the time required to execute the four bus cycle command necessary to program each byte. parameter symbols parameter description -150 unit jedec standard t avav t wc write cycle time min 150 ns t avel t as address setup time min 10 ns t elax t ah address hold time min 50 ns t dveh t ds data setup time min 50 ns t ehdx t dh data hold time min 0 ns t gldv t oeh output enable hold time for embedded algorithm min 10 ns t ghel read recovery time before write min 0 m s t wlel t ws we# setup time before ce# min 0 ns t ehwh t wh we# hold time min 0 ns t eleh t cp ce# pulse width min 50 ns t ehel t cph ce# pulse width high (note 3) min 20 ns t eheh3 embedded programming operation (notes 3,4) typ 9 max 300 m s t eheh4 embedded erase operation for each 64k byte memory sector (notes 1, 2) typ 1.5 max 15 s t vcs v cc setup time to write enable low min 50 m s
AMMCL00XA 29 preliminary ais memory map the ais (attribute information structure) is an area of memory used for storing information about the config- uration of the miniature card. the ais is recommended to be stored in the first sector of the first device of the flash array. as this area is not explicitly protected, the ais information must be reloaded onto the card in the event that the information is erased. the ais has five unique information areas: 1. identification data: this data includes manufacturer information (manufacturer and card name). 2. compatibility data: this data specifies basic infor- mation about the card (memory size, access time, memory type, power, etc.) 3. burst data (not applicable) 4. dram data (not applicable) 5. reserved data: this data area is reserved for future use. the ais supports up to four different memory technol- ogies on a card. some of the information areas are repeated in the memory map in order to specify dif- ferent technologies (see table 12). the technology count field in the identification data section defines the number of different technologies on a card. the first memory technology is defined in the ais memory map from address 40h through 7fh. the second memory technology is defined from 80h through bfh. the third memory technology is defined from c0h to dfh. the fourth memory technology is defined from e0h to ffh. the ais is stored as bytes within the 16-bit miniature card data word. the even byte d0Cd7 stores the ais data, and the odd byte d8Cd15 is reserved by the card manufacturer for manufacturing information. notes: 1. pa is address of the memory location to be programmed. 2. pd is data to be programmed at byte address. 3. d7 is the complement of the data written to the device. 4. d out is the data written to the device. 5. figure indicates last two bus cycles of four bus cycle sequence. 6. these waveforms are for the x16 mode. 21138e-13 figure 12. alternate ce# controlled write operation timings t wh t ws oe# ce# we# v cc t ds data t ah addresses t dh t cp pd dq7# d out t eheh3_or_4 t wc t as t cph t vcs xxxxh pa pa data# polling a0h t ghel
30 AMMCL00XA preliminary table 12. miniature card ais memory assignments * for more information on pc card compatibility refer to table 13 or the miniature card pc compatibility guide. note: not applicable indicates the address space does not apply to amd flash miniature cards, but is defined by mcif. card address section description 00hC0fh pc card compatibility area* reserved for pc card tuples 10hC1fh identification data identifies card type 20hC2fh identification data identifies card type 30hC3fh identification data identifies card type 40hC4fh compatibility data (area 1) memory technology #1 50hC5fh burst data (not applicable) 60hC6fh dram data (not applicable) 70hC7fh reserved for future use 80hC8fh compatibility data (not applicable) (memory technology #2) 90hC9fh burst data (not applicable) a0hCafh dram data (not applicable) b0hCbfh reserved for future use c0hCcfh compatibility data (not applicable) (memory technology #3) d0hCdfh reserved for future use e0hCefh compatibility data (not applicable) (memory technology #4) f0hCffh reserved for future use
AMMCL00XA 31 preliminary table 13. pc card compatibility memory assignments address values description 00h 01h tpl_code cistpl_device 01h 03h tpl_link 02h 53 device id 03h 2 mb = 7c, 4 mb = fc device size 04h ff end of cistpl_device 05h 1ch tpl_code cistpl_device_oc 06h 03h tpl_link 07h 53h device id 08h 2mb = 7c; 4mb = fc device size 09h ffh end of cistpl_device_oc 0ah 00h cistpl_null 0bh 00h cistpl_null 0ch 00h cistpl_null 0dh 00h cistpl_null 0eh 80h tpl_code cistpl_mini 0fh f0h tpl_link
32 AMMCL00XA preliminary identification data the identification data provides basic identification information about the card. this data section is required on all cards. table 14 shows the identification data for amds 3 volt-only miniature cards. compatibility data the compatibility data provides basic compatibility across all cards. this data section is required on all cards. the addresses in parentheses are specified for cards with more than one memory technology on the card. table 15 shows the compatibility data for amd 3-volt only miniature cards table 14. amd identification data card address value description 10h 99h miniature card identifier: fixed value for a host to identify an inserted miniature card 11h 11h level of compliance: defines the level of ais supported. the miniature cards described in this document are rev 1.1 compliant. 12h 78h or 76h ais checksum: the modulo-256 sum of all even bytes from 10hCffh. a valid checksum sums to 00h (2s complement). 9 2 mbyte card: 88h + 78h = 00h 4 mbyte card: 8ah + 76h = 00h 13h 41h manufacturer name : 13hC26h. string of ascii characters at addresses 13h to 26h to identify the manufacturer of the miniature card. ascii character a 14h 4dh ascii character m 15h 44h ascii character d 16h 20h ascii character - space 17h 49h ascii character - i 18h 4eh ascii character - n 19h 43h ascii character - c 1ah 00h ascii character - null 1bh 00h ascii character - null 1chC26h 00h unused space in manufacturer name field 27h 33h card name: (addresses 27hC3ah). string of ascii characters to identify the card name. ascii character 3 28h 56h ascii character v 29h 4dh ascii character m 2ah 43h ascii character c 2bh 20h ascii character - space 2ch 53h ascii character s 2dh 65h ascii character e 2eh 72h ascii character r 2fh 69h ascii character i 30h 65h ascii character e
AMMCL00XA 33 preliminary . note: all reserved bytes must be set to 00h. all reserved fields (bits) within bytes must be set to 0bh. all unused fields must be set to 00h. 31h 73h ascii character s 32h 00h ascii character - null 33hC3ah 00h unused space in card name field 3bh 01h technology count: defines the number of different memory technologies on the miniature card. technology count set to 1 3chC3fh 00h reserved space set to 00h; for future use table 14. amd identification data (continued) card address value description table 15. amd compatibility data card address value description 40h 00h defines the type of memory technology; flash = 000 binary 41h 01h device jedec manufacturer id 42h 38h device jedec component id: am29lv081 = 38h 43h 01h or 03h memory array size: 02 = 2 mbyte, 04 = 4 mbyte 44h 00h n/a 45h 0fh 3.3v access time: 150 ns 46h 00h n/a 47h 00h n/a 48h 24h typical read/write current at 3.3v: 20 ma read, 40 ma write (word mode) 49h 00h n/a 4ah 00h typical card standby current: 10 m a for 2 mbyte, 40 m a for 4 mbyte 4bhC4fh, 8chC8fh, cchCcfh, echCefh 00h reserved for future use 80hC8bh, c0Ccbh, e0hCebh 00h these addresses are designated for other memory technologies, which are not used in amd flash miniature cards. 100h 18h tpl_code cistpl_jedec_c 101h 02h tpl_link 102h 01h manufacturer id 103h 38h device id 104h 1eh tpl_code cistpl_devicegeo 105h 06h tpl_link 106h 02h dgtpl_bus: bus width 107h 01h dgtpl_ebs:11h = 64k byte erase block size 108h 01h dgtpl_rbs: read byte size 109h 01h dgtpl_wbs: write byte size 10ah 01h dgtpl_part: number of partition 10bh 01h fl device interleave: no interleave.
34 AMMCL00XA preliminary physical dimensions top view 38.00 mm 1.496 in. 33.00 mm 1.299 in. .118 in. 3.00 mm .189 in. 4.81 mm .118 in. 3.00 mm .118 in. 3.00 mm .118 in. 3.212 mm .217 in. 5.50 mm .217 in. 5.50 mm .161 in. 4.09 mm center line .284 in. 7.21 mm
AMMCL00XA 35 preliminary physical dimensions bottom view right side view write protect switch location 0.245 0.600 write protect switch location 0.245
36 AMMCL00XA preliminary revision history for AMMCL00XA distinctive characteristics added industrial temperature bullet. revised low power consumption specifications. deleted small form factor bullets. general description revised text to indicate that the miniature card specifi- cation will be defined by pcmcia. deleted references to the elastomeric connector. table 2, amd flash miniature cards and flash devices added wp as part of required base part number. miniature card pad assignments busy#: revised to indicate that the miniature card cannot accept most operations when busy# is low. cd#: deleted last sentence. ordering information added industrial temperature range. deleted np option from part number. added wp as part of required base part number. figure 2, host/card address assignments labeled host bus in drawing. deleted nc callouts in drawing. tables 5C9, command definitions revised for easier reference: removed h designators from table (now indicated in notes), removed 4-cycle reset/read command, separated read and reset commands, moved ra, rw, rd, pa, pw, pd, x, sa definitions to legend. moved erase suspend and erase resume definitions from table to notes. operating ranges added industrial temperature range. ac characteristics, write operations deleted t elqv , t avqv , t glqv , t elqx , t ehqz , t glqx , t ghqz , t axqx , t whgl , t glqnz embedded erase algorithm removed last paragraph. absolute maximum ratings revised storage and ambient temperature ratings. operating ranges added industrial temperature range. dc characteristics revised i cc specifications. added frequency specifica- tion to note 2. ac characteristics, write (erase/program) operations deleted t elqv , t avqv , t glqv , t elqx , t ehoz , t glox , t ghqz , t axq x, t whgl , t glqnz . table 19, amd compatibility data added two tuples of data to list, covering addresses 100hC10bh. trademarks copyright ? 1997 advanced micro devices, inc. all rights reserved. amd, the amd logo, and combinations thereof are trademarks of advanced micro devices, inc. product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

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